Dr. Tanuj Garg

Dr. Tanuj Garg

Assistant Professor
Department of Electronics & Communication Engineering
Gurukula Kangri (Deemed to be University), Haridwar, India

About

Overview

No about information provided.

Research Areas
Antenna Design, Substrate Integarted Waveguide, Leaky Wave Antenna,
Qualifications
Ph.D

Research Papers

5 entries
1
A novel broadband and high-gain compact annular ring microstrip antenna for satellite applications
Frequenz
2024 Index: Scopus, ESCI
DOI: https://doi.org/10.1515/freq-2023-0102 • ISSN: 2191-6349
2
Open Stop Band (OSB) Removal Techniques for SIW-Leaky Wave Antenna: A Review
Microwave Review
2023 Index: Scopus
DOI: 10.18485/mtts_mr.2023.29.2.5 • ISSN: 2406-1050
3
High Gain and Wide-Angle Continuous Beam Scanning SIW Leaky-Wave Antenna
Electronics
2023 Index: ESCI
4
SIW Leaky wave antenna for THz Applications
Electronics
2023 Index: ESCI
5
Leaky Wave Antenna: A Historical Development
Microwave Review
2021 Index: Scopus
ISSN: 2406-1050

Conference Papers

2 entries
1
Design and Analysis of Substrate Integrated Waveguide
International Conference on Sustainable Materials, Manufacturing And Energy Technologies
2022
2
Leaky wave Antenna: Past and Present
Integrated Intelligence Enable Networks and Computing
2020

Research Projects

1 entries
1
Beam Scanning rate enhancement in leaky wave antenna at X-Ku band at fixed frequency
Defence Research & Development Organisation (DRDO)
Completed
Grant: ₹33.43 Lakhs

Patents

1 entries
1
AN ANNULAR RING MICROSTRIP ANTENNA AND A METHOD FOR FORMING THE SAME
2022

Invited Lectures

5 entries
1
High Gain Miniaturized Wearable Narrowband Hexagonal Shaped antenna for ISM band applications
Faculty of Engineering & Technology, Gurukula Kangri (Deemed to be University), Haridwar
2
Multi-Band Leaky Wave Antenna Using SIW for Continuous Beam Scanning
Faculty of Engineering & Technology, Gurukula Kangri (Deemed to be University), Haridwar
3
Need of Low Power Simulations for Electronic Communication Systems
UPES, Bidholi Campus, Dehradun
4
Low Power Estimation for Multibit Memory Writing and Reading in Hardware Chip Design
Uttaranchal University,Dehradun
5
Design of 64-Bit Vedic Logic Adder and Multiplier for Low Power and Fast Switching of FPGA
Gurukula Kangri (Deemed to be University) Haridwar